(1) Field of the Invention
The present invention relates to the manufacture of very large (VLSI) and ultra large scale integrated (ULSI) circuits, and more particularly to the forming of a floating N/P/N and P/N/P structure used to protect circuits from plasma damage during the manufacture of the same.
(2) Description of the Related Art
It is known in the art of integrated circuit fabrication that metal or polysilicon lines are typically used to interconnect devices. The interconnections are formed by etching lines from blanket conductor layers. Usually plasma etch methods, such as but not limited to microwave plasma etch methods, reactive ion etch (RIE) plasma etch methods, magnetically enhanced reactive ion etch (MERIE) plasma etch methods and electron cyclotron resonance (ECR) plasma etch methods, are used for etching a blanket conductor layer to form a patterned conductor layer within an integrated circuit. It is also known that when blanket conductor layer and any other integrated circuit layers are exposed to the plasma etch method, they will typically become electrically charged. These metal or polysilicon layers and/or long interconnect lines which act like antennas, that may accumulate charge during plasma etching may be connected to the gate of the integrated circuit device. Because of the relatively high capacitance of the MOS devices, charge build-up occurs disproportionately at the gate of the MOS device. This plasma etch charge build-up can cause damage to the very thin gate oxide of the device. The detrimental effects of plasma charging are well known in the field. These include the formation of electron traps in gate oxide and displaced and implanted atoms at the material surface due to ion bombardment. The trapped charges decrease breakdown voltage of the oxide and if not annealed out, can cause shift in the threshold voltage resulting in reliability failures. Further, the surface states formed at the oxide-semiconductor interface degrade transistor characteristics such as subthreshold slope, transconductance, and device lifetime under hot electron stress. It is disclosed later in the embodiments of the present invention a plasma damage protection cell using floating N/P/N and P/N/P structure.
In prior art, several methods have been employed to protect devices against plasma damage. Diaz in U.S. Pat. No. 5,760,445 describes a protection device connected to a gate to minimize charge build-up during plasma processing. Thus in FIG. 1a, polysilicon gate (25), covering gate oxide (20) of the device to be protected is connected to an N-island (15) in a P-substrate (10) via metal line (30). The charge collecting material is represented by antenna (40). The N-island (15) and P-substrate (10) form diode (50) as shown schematically in FIG. 1b. As positive charge is deposited on gate oxide (20), excess charge accumulated on gate flows through diode (50). However, the diode breakdown voltages are generally greater than the failure voltages of the thin oxide they are protecting, rendering diode protection ineffective. To provide sufficient protection, larger area is needed.
Diaz in U.S. Pat. No. 5,760,445 shows an improved protection device which protects against charge build-up on a thin oxide gate during plasma etching. The protection device is described as a floating well PMOS device. When the PMOS transistor is formed, a lateral parasitic PNP transistor is formed. In the lateral PNP device the base is floating, the collector is connected to ground and the emitter is connected to the gates of the host PMOS protection device and the device to be protected. In operation, the gate of the PMOS transistor is tied to the source of the PMOS transistor so tat the PMOS transistor is off. Thus, the lateral PNP transistor controls the charging and discharging of the charge stored on the gate oxide. Excessive charge build-up is prevented by the breakdown voltage of the lateral PNP transistor. Because protection is achieved by PNP breakdown operation, the size of the PNP protection device can be substantially smaller than other protection devices.
In U.S. Pat. Nos. 5,866,482 and 5,767,006, Lee discloses the use of a blanket conductive layer to reduce charge damage. The conductive layer is formed over a semiconductor substrate. The blanket conductor layer communicates electrically with the semiconductor substrate in a manner such that an electrical charge is shunted form the blanket conductor layer into the semiconductor substrate when the blanket conductor layer is patterned to from the patterned conductor layer through the plasma etch method.
Su, et al., in U.S. Pat. No. 5,691,234, on the other hand, disclose a buried contact method to release plasma-induced charging damage on a device. In their method, a semiconductor substrate having a first conductivity type is provided. An oxide layer is formed in the oxide layer. A polysilicon layer is formed over the oxide layer and in the opening. A diffusion region is formed in the semiconductor substrate, connected to the polysilicon layer through the opening, having a second conductivity type opposite to the first conductivity type, whereby a buried contact is formed. The buried contact is connected, through the substrate, to a ground reference. Further processing in a plasma environment is performed that would normally produce charging damage to the integrated circuit; however, the buried contact prevents the charging damage.
Another method to provide tunnel oxide protection is disclosed by Cappelletti in U.S. Pat. No. 5,466,622. To form the protective diodes, a first polysilicon layer (poly1) is removed from the active areas in which the diodes are to be formed, using the same mask employed for shaping the poly1. Next, the interpoly dielectric layer and the gate oxide layer are removed from the active areas of the diodes, using the same mask employed for removing the dielectric layer from the transistor area. A second polysilicon layer (poly2) is deposited directly on to the active areas of the diodes; and the poly2 doping ions penetrate the active areas to form N+ regions which, together with the substrate, constitute the protection diodes.
In the present invention, a plasma damage protection cell with a floating N/P/N and P/N/P structure is disclosed which is tunable for different punch-through voltage levels and which provides low leakage.
It is therefore an object of this invention to provide a method of forming a plasma damage protection cell.
It is another object of this invention to provide a method of forming a floating N/P/N and P/N/P structure to serve as a plasma damage protection device.
It is still another object of this invention to provide a plasma damage protection cell using a floating N/P/N and P/N/P structure.
These objects are accomplished by providing a silicon substrate having a plurality of active and field regions defined; forming shallow trench isolation (STI) in said substrate; forming a gate oxide layer over said substrate; forming a polysilicon layer over said gate oxide layer; performing thin-film bipolar P-base implant; forming a polysilicon floating structure over said STI and a polysilicon floating gate over said gate oxide adjacent said STI; performing thin-film bipolar N-base implant; performing N/P lightly doped drain (LDD) implant; forming oxide spacer; performing N+ source/drain (S/D) and N+ emitter/collector (E/C) implant; performing P+ source/drain (S/D) and P+ emitter/collector (E/C) implant; forming interlevel dielectric layer and performing chemical-mechanical polishing (CMP); and forming contact pattern.
The objects of the present invention are further accomplished by providing a plurality of shallow trench isolation (STI) regions in a semiconductor substrate; an N/P/N floating structure partially covering said shallow trench isolation region, and partially N+ drain; said N/P/N floating structure having a base portion, an emitter portion, and a collector portion; a P/N/P floating structure partially covering said shallow trench isolation region, and partially P+ drain; said P/N/P floating structure having a base portion, an emitter portion, and a collector portion; an NMOS device protected by said N/P/N floating structure; and a PMOS device protected by said P/N/P floating structure.